1. Field of the Invention
The present invention relates to a microcomputer system including a microprocessor and a memory.
2. Description of related art
At present, the performance of microprocessors has been greatly improved by an operation frequency increased by improvement in semiconductor device manufacturing processes and by improvement in architecture such as pipelined systems. Therefore, the current processors can execute given instructions at a very high speed. However, considering a microcomputer system having a microprocessor as a central device and other peripheral input/output devices, a remarkable improvement cannot be found out in the performance of the overall microcomputer system for the following reason: Although the microprocessor itself can operate at a very high speed, since the speed of access to the memory is limited, the fetch of instruction codes cannot follow the execution of instructions in the microprocessor. Specifically, a so-called "bus neck" will occur.
If the bus neck occurs, not only the advantage of the prefetch of instruction codes given by an instruction queue cannot obtained, but also the instruction execution itself of the microprocessor is put in a wait condition for shortage of instruction codes in the instruction queue. Alternatively, if the fetch cycle for instruction codes is preferentially started, the data read/write cycle to be executed with execution of an instruction will be delayed, with the result that the time of instruction execution will be elongated. The above defects will waste the hardware resource for execution of instruction, and will decrease the performance of the overall system.
Furthermore, it is necessary to provide additional circuits such as latches and drivers between the microprocessor and the memory chip. This will decrease the economic efficiency of the system, and the increase of the number of parts will also decrease the reliability of the system.